- TSV Interposer
Interposer process flow
Specification
Layer | Parameter | TSV Interposer |
Silicon | Size | 200mm |
TSV | Via Diameter | 50 ~ 100 ㎛ |
Via Depth | 150 ~ 250 ㎛ | |
Via Pitch | ≥100 ㎛ | |
AR | ≤3 : 1 @70um via | |
Insulator | SiO2, SiNx (option) | |
Cu Fill | Full Fill | |
Passivation | Material | Polyimide |
Thickness | ≥5㎛ | |
RDL Metal | Material | Copper |
Thickness | ≥5 ㎛ | |
L/S | 10 / 10㎛ | |
Solder Bump | Material | SnAg |
Ball Size | Below 250 ㎛ | |
Height | Below 200 ㎛ |
Feature
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– TSV and Multilayer Redistributed Cu with Passivation
– Through Via architecture
– Available on 8inch Si wafer
– Single and Both Redistribution Layers on Cu/PI
– 150㎛ ~ 250㎛ Si Thickness
– Typical Via Diameter is 50㎛ ~ 100㎛ with AR 3:1
– Process : Via First → Grinding → Dual Plating
Customizing FAB service : Equipment infrastructure
Process | Equipment | Wafer Size | Type | Material | |||
200mm | 300mm | Flat | Notch | Silicon | Glass | ||
Lihtography | Stepper | ○ | ○ | ○ | ○ | ○ | |
Manual Coating | ○ | ○ | ○ | ○ | ○ | ○ | |
Coater | ○ | ○ | ○ | ○ | ○ | ||
Via etching | Deep Si Etcher | ○ | ○ | ○ | ○ | ||
Via Isolation | Furnace(Only oxide) | ○ | ○ | ○ | ○ | ||
PE-CVD | ○ | ○ | ○ | ○ | |||
Metallization | PVD(Sputter) | ○ | ○ | ○ | ○ | ○ | ○ |
Electro plating | ○ | ○ | ○ | ||||
Etching | ICP Etcher / Ashing | ○ | ○ | ○ | ○ |